A conventional leadless multi-chip electronic module is generally designated by the reference numeral 10 in FIGS. 1A and 1B. Referring to FIGS. 1A-1B, the module 10 (which may be QFN or PQFN devices, for example) comprises two or more integrated circuit (IC) chips 12, 14, metal leadframe bond pads 16a-16d and a substrate 18. Large bond pads 16a, 16b are provided for each IC chip 12, 14; and a plurality of signal bond pads 16c and power bond pads 16d are provided to interface the IC chips 12, 14 to the substrate 18. Terminals on the exposed face of the IC chips 12 and 14 are electrically coupled to the signal and power bond pads 16c and 16d by wirebonds 20, as shown. A plastic or epoxy encapsulant 22 covers the IC chips 12 and 14, the upper and lateral surfaces of the leadframe bond pads 16a-16d and the wirebonds 20, leaving only the lower surfaces of the leadframe bond pads 16a-16d uncovered. Following singulation of the leadframe bond pads 16a-16d, their exposed lower surfaces are soldered to a set of conductor pads 24 formed on the inboard face 18a of substrate 18.
Due to leadframe layout considerations, a conventional leadless multi-chip electronic module 10 is generally configured with the large IC bond pads 16a and 16b occupying a central region of the module 10, and the signal and power bond pads 16c and 16d occupying the peripheral or marginal region of the module 10. In the illustration of FIG. 1A, for example, the signal and power bond pads 16c and 16d are respectively disposed along the top and bottom edges of the module 10, with the IC bond pads 16a and 16b disposed in a central region between the signal and power bond pads 16c and 16d. While this sort of layout is desirable from a manufacturing standpoint, it can cause reliability problems in applications where the module 10 is used in environments subject to widely varying ambient temperatures such as occur in outdoor or vehicular systems. In such environments, the CTE (coefficient of thermal expansion) differences between the leadframe elements 16a-16d and the substrate 18 can result in solder joint cracking, particularly in the case of small solder joints 26 between the substrate 18 and the signal bond pads 16c located at the periphery of the module 10. Solder joints 26 located at or near the corners of the module 10 are particularly vulnerable to thermal-related failures.
A typical way of improving solder joint reliability is to increase the surface area of the signal bond pads 16c located at the periphery of the module 10, particularly in the corners, as illustrated in FIG. 1A. However, increasing the bond pad surface area limits the pin-count of the module 10, and only marginally improves the solder joint reliability. Accordingly, what is needed is a way of significantly improving the solder joint reliability of a leadless multi-chip electronic module.